About Simulation¶

Directory simulation contains two different kinds of simulation environments.

rtl:

simulation environments for RTL-level inputs
netlist:

simulation environments netlist-level inputs

RTL-Level Simulation ENV¶

TO BE ADDED

Netlist-Level Simulation ENV¶

TO BE ADDED

Existing Environments¶

Information on several existing environments is listed below.

rtl_calc_add_knl¶

Function
1. elaborate RTL design calc_add_knl
2. check RTL design calc_add_knl
3. simulate RTL design calc_add_knl
4. collect coverage of RTL design calc_add_knl
5. do simulation regression on RTL design calc_add_knl
6. do coverage regression on RTL design calc_add_knl
Pre-Request

item

my version

make

3.82

ncverilog

15.20-s083

verdi

2019.06-SP2

simvision

2019.06-SP2

imc

21.09-s005

Content

item	description	postscript
script/makefile.mk	mother makefile
script/uniqFileList.pl	script to uniq file lists
script/regression.sh	regression script
rtl_calc_add_knl/makefile	daughter makefile
rtl_calc_add_knl/sim_calc_add_knl.f	simulation files lists
rtl_calc_add_knl/sim_calc_add_knl.v	mother testbench
rtl_calc_add_knl/sub_bench	directory for daughter testbench
rtl_calc_add_knl/check_data	directory for test vectors
rtl_calc_add_knl/simul_data	directory for simulation or coverage data	generated by command make sim or make cov
rtl_calc_add_knl/simul_data_regr	directory for regression data	generated by command make sim_regr or make cov_regr

Usage

In the Linux server, change the directory to simulation/rtl/rtl_calc_add_knl,

then you can
1. view help with
```
make
```
  then you will get
2. view elaboration results with
```
make com_view
```
  then you will get
3. view check results with
```
make chk_view EDA_CSTR_TOOL=syn
```
  then you will get
4. simulate and dump waveform with
```
make sim SIM_KNOB_WAVEFORM=1
```
  then you will get
5. view simulation results (waveform) with
```
make sim_view
```
  then you will get
6. collect coverage with
```
make cov
```
  then you will get
7. view coverage results with
```
make cov_view
```
  then you will get
  
  Since only one saturation mode (FLAG_SAT==1) is tested, the coverage grade is less than 100%.
8. do simulation regression with
```
make sim_regr
```
  then you will get
  
  Since 2 correct cases and 2 wrong cases are “regressioned”, run/skip/error/all number 4/0/2/4 is reported.
9. view simulation regression results with
```
make sim_regr_view
```
  then you will get
10. do coverage regression with
```
make cov_regr
```
  then you will get
  
  Since only correct cases are “regressioned” thanks to T_V_CSTR_PATTERN, run/skip/error/all number 2/0/0/2 is reported.
11. view coverage regression results with
```
make cov_regr_view
```
  then you will get
  
  Since both saturation modes (FLAG_SAT==0 and FLAG_SAT==1) are tested, the coverage grade is 100%.
12. view configuration value with
```
make cfg_view
```
  then you will get
13. clean files with
```
make clean
```
  or
```
make clean_all
```
  then you will get