About Source

Directory source contains four different kinds of design files.

• common:

  commonly-used design files

• */kernel:

  kernel-related design files used in design * (for example, calculator or xkcdc)

• */interface:

  interface-related, pre-process-related or post-process-related design files used in design * (for example, calculator or xkcdc)

• */memory:

  memory instantiations of different technologies (for example, TSMC65 or GF28) used in design * (for example, calculator or xkcdc)

Common

Directory common contains design files like

• register-based single-port SRAMs (with or without byte enable)

• register-based two-port SRAMs

• register-based ack-type FIFOs

• register-based req-type FIFOs

• register-based delayers

Before Introduction to Kernel and Interface

In order to illustrate the contents contained in directory kernel and interface, I would like to give a simple introduction to design add and design xkcdc.

The former is a simple combination of adder, substrator, multiplier, and dividor, while the latter is a complex video encoder.

• calculator

  

  • APB: APB-bus-to-register-access convertor

  • AXI: data-access-to-AXI-bus convertor

  • FTH: fetch

  • ADD: adder

  • SUB: substrator

  • MUL: multiplier

  • DIV: dividor

  • DMP: dump

• xkcdc

  

  • APB: APB-bus-to-register-access convertor

  • AXI: data-access-to-AXI-bus convertor

  • SCL: scaler

  • OSD: on-screen display

  • FTH: fetch

  • RMD: rough mode decision

  • IME: integer motion estimation

  • FME: fractional motion estimation

  • RDO: rate-distortion optimization

  • REC: reconstruction

  • DBF: de-blocking filter

  • SAO: sample-adaptive offset

  • E_C: entropy encoding

  • DMP: dump

*/Kernel

Directory kernel contains all kernel-related design files.

In design calculator, the following modules belongs to the kernel part since they belong to the core processing

• FTH

• ADD

• SUB

• MUL

• DIV

• DMP

Due to the same reason, the following modules belongs to the kernel part of design xkcdc

• FTH

• RMD

• IME

• FME

• RDO

• REC

• DBF

• SAO

• E_C

• DMP

*/Interface

Directory kernel contains all interface-related design files.

In design calculator, the following modules belongs to the interface part since they either do the job of interface converting or belong to the pre/post-processing

• APB

• AXI

Due to the same reason, the following modules belongs to the kernel part of design xkcdc

• APB

• AXI

• SCL

• OSD

*/Memory

Directory memory contains memory instantiations of different technologies, which is managed with perl scripts.

Naming Rule

All codes in design files use this naming rule

[<(hierachy|tag)>_]<type>_<object>_<modifier0>_..._<modifierN>_[s?_][d?_][(i|o|w|r)]

1. <(hierachy|tags)> refer to the short name of hierarchies or tags, which usually use 3 letters.

   For example,

   wires directly connected to module calc_add_top can be prefixed with ADD_; variables related to adding logic can be prefixed with add_;

   wires directly connected to module calc_sub_top can be prefixed with SUB_; variables related to substrating logic can be prefixed with sub_;

   wires directly connected to module calc_mul_top can be prefixed with MUL_; variables related to multiplying logic can be prefixed with mul_;

   wires directly connected to module calc_div_top can be prefixed with DIV_; variables related to dividing logic can be prefixed with div_;

   wires directly connected to module calc_reg can be prefixed with REG_;

   wires directly connected to module calc_knl_top can be prefixed with KNL_;

   wires directly connected to module calc_itf_top can be prefixed with ITF_;

2. <type> includes the following items, which use 3 letters.

   <type>	description	postscript
   flg	enabling	enabled if configured with 1
   num	number
   siz	size
   cnt	counter
   idx	index
   enm	enumerator
   dat	value

3. <object> refer to the short name of objects. For example,

   <object>	description
   frame	frame
   unit	unit
   reg	register
   scl	scaler
   delay	delay

4. <modifier> refer to the short name of modifiers, which usually use 3 letters. For example,

   <modifier>	description
   max	maximum
   min	minimum
   bfr	before
   aft	after
   in	input
   out	output

5. s? and d? refer to the short name of the ?th stage or delay respectively.

6. (i|o|w|r) refer to the short name of input, output, wire or reg respectively.

7. special cases

   • FSM: cur_state_r and nxt_state_w are adopted

   • counter done: cnt_done_w is adopted

Hierarchy

1. The hierarchy of design files contains three levels, which are top level, interface/kernel level, and module level.

   • In general, top-level design files contain only one file, which is the top of the whole design,

     for example, calc_top.v or xkcdc_top.v
   • In general, kernel/interface-level design files contain only two files which are the top of interface-related and kernel-related design files,

     for example, calc_knl_top.v and calc_itf_top.v or xkcdc_knl_top.v and xkcdc_itf_top.v
   • Module-level design files contain all design files related to the current module.

     For example, module RMD (rough mode decision) in design xkcdc contains

     • cdc_rmd_top.v: top of RMD

     • cdc_rmd_ctl.v: logic to do control

     • cdc_rmd_ref.v: buffer for reference pixels and logic to do reference management

     • sram_sp_cdc_rmd_ref_buf_ref.v: wrapper for the single-port SRAM instantiated in cdc_rmd_ref.v to buffer reference pixels

     • cdc_rmd_pre.v: wrapper for prediciton modules

     • cdc_rmd_pre_knl.v: logic to do prediction

     • cdc_rmd_res.v: logic to do residual calculation

     • cdc_rmd_cst.v: wrapper for cost calculation moduels

     • cdc_rmd_cst_knl.v: logic to do cost calculation

     • cdc_rmd_cmp.v: logic to do comparison

2. The hierarchy of memory instantiations also have three levels, which are memory-wrapper level, definition level, and instantiation level.

   <module_name>
   └── <memroy_type>_<design_name>_buf_<content_name>.v
          └── definitions
                 └── instantiations
   

   For example, one buffer which stores reference pixels is need in module cdc_rmd_ref.v, hierachy of which would be

   *cdc_rmd_ref.v*
   └── *sram_sp_cdc_rmd_ref_buf_ref.v*
          ├── `KNOB_LIB_BEHAVE
          │      └── sram_sp_behave.v
          ├── `KNOB_LIB_FPGA
          │      └── FPGA_INST_SRAM_SP_CDC_RMD_REF_BUF_REF_1024X32.v
          └── `KNOB_LIB_ASIC
                 └── ASIC_INST_SRAM_SP_CDC_RMD_REF_BUF_REF_1024X32.v
   

   Noting that modules in the instantiation level would be marked with the implementation platform, design, buffer content, and size.

   Here are the detailed contents of sram_sp_cdc_rmd_ref_buf_ref.v

   • sram_sp_cdc_rmd_ref_buf_ref.v

     overview

     
     
     
     
     

Detailed Rules

Contents of cdc_rmd_top.v, cdc_rmd_ctl.v and cdc_rmd_cst_knl.v are provided to illustrate the detailed rules of design codes.

• cdc_rmd_top.v

  overview

  
  
  
  
  
  
  
  
  
  
  
  
  
  

• cdc_rmd_ctl.v

  overall

  
  
  
  
  
  
  

• cdc_rmd_cst_knl.v

  overall